Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-04-24

2009-02-10

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S390000, C257S758000

Reexamination Certificate

active

07489010

ABSTRACT:
In a semiconductor memory device with NAND cell units arranged, two first select gate lines in adjacent blocks sandwiching a bit line contact are formed to have first connection portions disposed at a certain pitch, where the two first select gate lines are connected to each other; two second select gate lines in adjacent blocks sandwiching a source line contact are formed to have second connection portions disposed at substantially the same pitch as the first connection portions, where the two second select gate lines are connected to each other; and the first and second shunt wirings are contacted with the first and second select gate lines at the first and second connection portions, respectively.

REFERENCES:
patent: 6240012 (2001-05-01), Nakamura et al.
patent: 6424588 (2002-07-01), Nakamura et al.
patent: 6611447 (2003-08-01), Nakamura et al.
patent: 6836444 (2004-12-01), Nakamura et al.
patent: 2002/0114191 (2002-08-01), Iwata et al.
patent: 2001-308206 (2001-11-01), None
U.S. Appl. No. 11/235,206, filed Sep. 27, 2005, Yasushi Kameda, et al.

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