Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2005-12-12
2009-08-04
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S763000
Reexamination Certificate
active
07571379
ABSTRACT:
A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.
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European Search Report; EP 05 42 5233; Sep. 14, 2005.
STMicroelectronics; “Datasheet: 8-Bit Intelligent Controller Unit (ICU) Two Timer/PWMs. ADC, I2C, SPI, SCI”; XP-002344784; http://www.st.com/stonline/products/literature/ds/8793.pdf; May 2004; retrieved online Sep. 14, 2005.
Adamo Santi Carlo
Aureliano Gianluca Vincenzo
Bombaci Francesco
Critelli Rosalino
Chase Shelly A
Hogan & Hartson LLP
STMicroelectronics S.r.l.
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