Method and system to optimize timing margin in a system in...

Details Method and system to optimize timing margin in a system in... Method and system to optimize timing margin in a system in...

2006-01-03

2009-08-11

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07574687

ABSTRACT:
In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are transmitted to serpentine traces located on a Printed Circuit Board (PCB) which adjusts the active edge of one signal relative to another signal. The serpentine trace introduces a delay in the clock signal thereby optimizing timing margins. By providing access to signals otherwise internal the SiP, testing and signal verification is also simplified.

REFERENCES:
patent: 4942373 (1990-07-01), Ozawa et al.
patent: 6446249 (2002-09-01), Wang et al.
patent: 7450535 (2008-11-01), Best
Lawrence Golick, et al, “EETimes.com—SiP Models call for right blend of tech” 2 pages, May, 10, 2004.
Manoz Krovvidy, et al “DDR Timing Closure: Physical Design and STA Methodology”, 31 pages. 2003, Snug, Boston.

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