Virtual power rails for integrated circuits

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S049110, C365S196000

Reexamination Certificate

active

07542329

ABSTRACT:
Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.

REFERENCES:
patent: 4623989 (1986-11-01), Blake
patent: 6724648 (2004-04-01), Khellah et al.
patent: 6728130 (2004-04-01), Afghahi et al.
patent: 6798682 (2004-09-01), Chuang et al.
patent: 6801463 (2004-10-01), Khellah et al.
patent: 2002/0122329 (2002-09-01), Ma et al.
patent: 2004/0100815 (2004-05-01), Ye et al.
patent: 2004/0125681 (2004-07-01), Yamaoka et al.
patent: 2006/0002223 (2006-01-01), Song et al.
patent: 2006/0232321 (2006-10-01), Chuang et al.
patent: 2007/0189102 (2007-08-01), Lin et al.
patent: 1725373 (2006-01-01), None
M. D. Powell, S.-H. Yang, B. Falsafi, K. Roy, & T. N. Vijaykumar, “Gated Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” in Proc. ISLPED, Jul. 2000, pp. 90-95.
C. H. Kim & K. Roy, “Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors,” ISLPED 2002: 251-254.
A. Agarwal, H. Li, & K. Roy, “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron,” Solid-State Circuits, IEEE Journal of, pp. 319-328, vol. 38, Issue: 2, Feb. 2003.
P. Elakkumanan, A. Narasimhan, & R. Sridhar, “NC-SRAM—A Low-Leakage Memory Circuit for Ultra-Deep Submicron Designs”, Proceedings, IEEE International SoC Conference 2003, Portland, OR, Sep. 2003, pp. 3-6.
N. Hanchate & N. Ranganathan, “LECTOR: A Technique for Leakage Reduction in CMOS Circuits,” IEEE Trans. VLSI Syst., vol. 12, Issue: 2, 2004, pp. 196-205.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Virtual power rails for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Virtual power rails for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual power rails for integrated circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4071659

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.