Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-02-21
2009-11-10
Baderman, Scott T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S006130
Reexamination Certificate
active
07617437
ABSTRACT:
A device for error correction includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection information for the memory location is not available, such as after a reset or power-on event. In addition, the memory control module can promote partial write requests to full write requests when error processing is disabled to ensure that valid error detection and correction data is calculated for the memory location. By disabling error processing until valid error detection and correction information is available, the number of unnecessary or invalid error processing operations is reduced, thereby conserving device resources.
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patent: 6119248 (2000-09-01), Merkin
patent: 2005/0283650 (2005-12-01), Zhang et al.
patent: 2006/0143551 (2006-06-01), Biswas et al.
patent: 2008/0148124 (2008-06-01), Zhang et al.
PCT/US07/60659 International Search Report and Written Opinion mailed Aug. 19, 2008.
Baderman Scott T
Freescale Semiconductor Inc.
Rizk Sam
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