Circuit technique to prevent device overstress

Details Circuit technique to prevent device overstress Circuit technique to prevent device overstress

2005-12-08

2009-11-17

Pascal, Robert (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C327S309000

Reexamination Certificate

active

07619444

ABSTRACT:
Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.

REFERENCES:
patent: 6118303 (2000-09-01), Schmitt et al.
patent: 6130556 (2000-10-01), Schmitt et al.
patent: 6335637 (2002-01-01), Correale et al.
patent: 6744298 (2004-06-01), Yamauchi et al.
patent: 7002379 (2006-02-01), Ajit

Affiliated with

Also associated with

Rating

Circuit technique to prevent device overstress does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit technique to prevent device overstress, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit technique to prevent device overstress will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4069948