Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-06
2009-11-03
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07614024
ABSTRACT:
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.
REFERENCES:
patent: 4615011 (1986-09-01), Linsker
patent: 5225771 (1993-07-01), Leedy
patent: 5742099 (1998-04-01), Debnath et al.
patent: 5801432 (1998-09-01), Rostoker et al.
patent: 6202191 (2001-03-01), Filippi et al.
patent: 6226782 (2001-05-01), Nowak et al.
patent: 6242767 (2001-06-01), How et al.
patent: 6305000 (2001-10-01), Phan et al.
patent: 6510545 (2003-01-01), Yee et al.
patent: 6528883 (2003-03-01), Dunham et al.
patent: 6532581 (2003-03-01), Toyonaga et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
patent: 6711727 (2004-03-01), Teig et al.
patent: 6748579 (2004-06-01), Dillon et al.
patent: 6847853 (2005-01-01), Vinciarelli et al.
patent: 7089522 (2006-08-01), Tan et al.
patent: 7102237 (2006-09-01), Dellinger
patent: 7146593 (2006-12-01), Travis et al.
patent: 7222322 (2007-05-01), Chyan et al.
patent: 7240314 (2007-07-01), Leung
patent: 7328419 (2008-02-01), Vuong et al.
patent: 2002/0078425 (2002-06-01), Mehrotra et al.
patent: 2005/0044517 (2005-02-01), Seaman et al.
patent: 2006/0081988 (2006-04-01), Dunham et al.
patent: 2006/0265684 (2006-11-01), Buehler et al.
Broadcom Corporation
Garlick & Harrison & Markison
Levin Naum B
Rudnick Holly L.
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