Power throttling in a memory system

Details Power throttling in a memory system Power throttling in a memory system

2005-10-12

2009-02-24

Portka, Gary J (Department: 2188)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S310000, C713S320000, C713S323000, C711S005000, C711S104000, C711S105000, C711S106000

Reexamination Certificate

active

07496777

ABSTRACT:
A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time. In response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state. The specified window of time may be either a specified number of memory refresh intervals or buffer sync intervals. The memory controller maintains a count of memory refresh or buffer sync intervals.

REFERENCES:
patent: 6247084 (2001-06-01), Apostol et al.
patent: 6295586 (2001-09-01), Novak et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6571325 (2003-05-01), Satagopan et al.
patent: 6608476 (2003-08-01), Mirov
patent: 6725314 (2004-04-01), Dong
patent: 6845457 (2005-01-01), Mirov
patent: 6882082 (2005-04-01), Greeff et al.
patent: 6922770 (2005-07-01), Shanmugasundaram et al.
patent: 6941428 (2005-09-01), Carr
patent: 7017022 (2006-03-01), Jeddeloh
patent: 7032092 (2006-04-01), Lai
patent: 7051151 (2006-05-01), Perego
patent: 2004/0030794 (2004-02-01), Hugly et al.
patent: 2004/0114448 (2004-06-01), Johnson et al.
patent: 2004/0183795 (2004-09-01), Deering et al.
patent: 2004/0260957 (2004-12-01), Jeddeloh et al.
patent: 2005/0198458 (2005-09-01), Cho
patent: 2006/0020740 (2006-01-01), Bartley et al.
patent: 2006/0024541 (2006-02-01), Weiss et al.
patent: 2 416 056 (2006-01-01), None
patent: WO 2004/109528 (2004-12-01), None
patent: WO 2005/066965 (2005-07-01), None
Delaluz et al. (DRAM Energy Management Using Software and Hardware Directed Power Mode Control, 2001 IEEE, ISBN: 0-7695-1019-1/01), pp. 159-169.
U.S. Appl. No. 11/124,848, filed May 9, 2005.
U.S. Appl. No. 11/304,166, filed Dec. 15, 2005.
U.S. Appl. No. 11/205,706, filed Aug. 17, 2005.
U.S. Appl. No. 10/975,650, filed Oct. 28, 2004.
U.S. Appl. No. 10/989,577, filed Nov. 16, 2004.
Fully Buffered DIMM (FB-DIMM) Server Memory Architecture: Capacity, Performance, Reliability and Longevity- Feb. 18, 2004- Retrieved from http://www.idt.com/content/OSA—FB-DIMM-arch.pdfVOGT-Note connections of FB-DIMM's on p. 9.

Affiliated with

Also associated with

Rating

Power throttling in a memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power throttling in a memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power throttling in a memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4068551