Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-15
2009-06-09
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S127000, C711S128000, C711S133000
Reexamination Certificate
active
07546417
ABSTRACT:
A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags. Similarly, an access address tag is divided into an address common subtag and address remaining tag. When the index of an access address selects a set, a match comparison of the address common subtag and the selected set common subtag is performed. Also, the address remaining tag and selected set remaining subtags are compared for matching before the selected set and associated data is supplied to the requester.
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Jeffrey Rothman and Alan Smith;Sector Cache Design and Performance, in Proceedings of Mascots 2000.
Rajamony Ramakrishnan
Speight William Evan
Zhang Lixin
Bertram Ryan
Ellis Kevin L
International Business Machines - Corporation
Shimokaji & Associates P.C.
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