Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-03-20
2009-06-09
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000, C326S081000, C326S083000, C326S038000
Reexamination Certificate
active
07545177
ABSTRACT:
Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.
REFERENCES:
patent: 6208171 (2001-03-01), Kumagai et al.
patent: 6239614 (2001-05-01), Morikawa
patent: 6529042 (2003-03-01), Hiramoto et al.
patent: 6768335 (2004-07-01), Young et al.
patent: 6768338 (2004-07-01), Young et al.
patent: 6949951 (2005-09-01), Young et al.
patent: 7053654 (2006-05-01), Young et al.
patent: 7279926 (2007-10-01), Severson et al.
patent: 2001/0052800 (2001-12-01), Mizuno
patent: 2003/0218478 (2003-11-01), Sani et al.
patent: 2006/0114025 (2006-06-01), Frenkil et al.
patent: 2007/0047364 (2007-03-01), Chuang et al.
patent: 2007/0085567 (2007-04-01), Berthold et al.
patent: 2007/0159239 (2007-07-01), Rhee
patent: 2007/0168899 (2007-07-01), Frenkil
patent: 2007/0176642 (2007-08-01), Kursun et al.
patent: 2007/0279100 (2007-12-01), Fallah et al.
Anantha Chandrakasan et al.;Design of High-Performance Microprocessor Circuits; Chapter 3: “Techniques for Leakage Power Reduction”; IEEE Press; Oct. 2000; pp. 46-62.
Kaushik Roy et al.; “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”; Copyright 2003 IEEE; Proceedings of the IEEE, vol. 91, No. 2; Feb. 2003; pp. 305-327.
James w. Tschanz et al.; “Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”; Copyright 2003 IEEE; IEEE Journal of Solid-State Circuits, vol. 38, No. 11; Nov. 2003; pp. 1838-1845.
Changbo Long et al.; “Distributed Sleep Transistor Network for Power Reduction”; Copyright 2004 IEEE; IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, No. 9; Sep. 2004; pp. 937-946.
Pietro Babighian et al.; “Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating”; Copyright 2004 IEEE; Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (Date'04); pp. 1-2, month unknown.
Tim Tuan et al.; “A 90nm Low-Power FPGA for Battery-Powered Applications”; FPGA'06; Copyright 2006 ACM; Feb. 22-24, 2006; pp. 1-9.
U.S. Appl. No. 10/783,216, filed Feb 20, 2004, Tuan et al.
U.S. Appl. No. 10/783,589, filed Feb. 20, 2004, Look et al.
U.S. Appl. No. 11/196,179, filed Aug. 3, 2005, Rahman et al.
Kao Sean W.
Rahman Arifur
Tuan Tim
Hardaway Michael R.
Tan Vibol
Wallace Michael T.
Xilinx , Inc.
LandOfFree
Method and apparatus for leakage current reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for leakage current reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for leakage current reduction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4066643