Semiconductor device having a pad metal layer and a lower...

Details Semiconductor device having a pad metal layer and a lower... Semiconductor device having a pad metal layer and a lower...

2004-04-13

2009-12-15

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S774000, C257SE21508, C257SE21509, C257SE21519

Reexamination Certificate

active

07632749

ABSTRACT:
A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

REFERENCES:
patent: 5248903 (1993-09-01), Heim
patent: 5736791 (1998-04-01), Fujiki et al.
patent: 6756675 (2004-06-01), Tanaka
patent: 6765228 (2004-07-01), Lin et al.

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