Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2004-06-10
2009-02-03
Awad, Amr (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
07486269
ABSTRACT:
A shift register includes a plurality of stages to generate a plurality of output signals, in sequence. Each of the stages includes a driving circuit, a charging circuit, a discharging circuit and a holding circuit. The driving circuit is configured to generate a first output signal in response to a first clock signal or a second clock signal having a phase different from the first clock signal. The charging circuit is configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage. The discharging circuit is configured to discharge the electric charge in response to a third output signal of an adjacent next stage. The holding circuit is configured to maintain the first output signal within a first voltage when the first output signal is in an inactive state. Therefore, a parasite capacitance is decreased to prevent a floating of a pull-up transistor.
REFERENCES:
patent: 6300928 (2001-10-01), Kim
patent: 6556646 (2003-04-01), Yeo et al.
patent: 6789514 (2004-09-01), Suh et al.
patent: 7042430 (2006-05-01), Isami et al.
Awad Amr
Cantor & Colburn LLP
Samsung Electronics Co,. Ltd.
Willis Randal
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