Electrical computers and digital processing systems: processing – Processing control – Logic operation instruction processing
Reexamination Certificate
2002-10-22
2009-12-15
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Logic operation instruction processing
C712S244000, C710S262000
Reexamination Certificate
active
07634638
ABSTRACT:
An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.
REFERENCES:
patent: 3828327 (1974-08-01), Berglund et al.
patent: 4400769 (1983-08-01), Kaneda et al.
patent: 4949238 (1990-08-01), Kamiya
patent: 5109489 (1992-04-01), Umeno et al.
patent: 5148544 (1992-09-01), Cutler et al.
patent: 5210874 (1993-05-01), Karger
patent: 5345567 (1994-09-01), Hayden et al.
patent: 5381540 (1995-01-01), Adams et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5621886 (1997-04-01), Alpert et al.
patent: 5623636 (1997-04-01), Revilla et al.
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5655135 (1997-08-01), Sholander et al.
patent: 5701493 (1997-12-01), Jaggar
patent: 5701501 (1997-12-01), Gandhi
patent: 5740451 (1998-04-01), Muraki et al.
patent: 5742780 (1998-04-01), Caulk, Jr.
patent: 5764969 (1998-06-01), Kahle et al.
patent: 5768599 (1998-06-01), Yokomizo
patent: 5805918 (1998-09-01), Blomgren et al.
patent: 5887175 (1999-03-01), Col et al.
patent: 5911065 (1999-06-01), Williams et al.
patent: 6061709 (2000-05-01), Bronte
patent: 6249881 (2001-06-01), Porten et al.
patent: 6282657 (2001-08-01), Kaplan et al.
patent: 6341324 (2002-01-01), Caulk et al.
patent: 6393556 (2002-05-01), Arora
patent: 6397379 (2002-05-01), Yates et al.
patent: 6496912 (2002-12-01), Fields et al.
patent: 6532533 (2003-03-01), Bhandal et al.
patent: 6560698 (2003-05-01), Mann
patent: 6666383 (2003-12-01), Goff et al.
patent: 6732298 (2004-05-01), Murthy et al.
patent: 6763450 (2004-07-01), Miyaguchi et al.
patent: 6772326 (2004-08-01), Chauvel et al.
patent: 6779065 (2004-08-01), Murty et al.
patent: 6820153 (2004-11-01), Yanagi et al.
patent: 6842811 (2005-01-01), Barry et al.
patent: 7181600 (2007-02-01), Uhler
patent: 7185183 (2007-02-01), Uhler
patent: 2002/0016883 (2002-02-01), Musoll et al.
Weaver, David L., Germond, Tom. “The SPARC Architectural Manual.” Version 9. SPARC International, Inc. 1994.
RISC Microprocessor Databook, 32-Bit TX System RISC TX39 Family TX39/H2 Processor Core, Chapter 1-8, Appendix A, Doc. ID 4412D-9908 (1998).
Toshiba Data sheet List;http://www.seicon.toshiba.co/jp/eng/prd/micro/td/td—all.html; Toshiba Semiconductor Company.
Alpha Architecture Handbook (Oct. 1996). pp. 11-2 and C-20.
CompactRISC CR16A Programmer's Reference Manual (Feb. 1997); pp. 2-6, 3-3, 5-12, and 5-13.
Richard L. Sites, Richard T. Witek, Alpha AXP Architecture Reference Manual Second Edition, Copyright 1995, p. 2-19.
U.S. Appl. No. 09/592,106, filed Jun. 12, 2000, Melvin et al.
Alpha Architecture Handbook (Oct. 1996). Digital Equipment Corporation. Maynard, Massachusetts.
Intel,IAPX88 Book with an Introduction to the IAPX88, 1983, INTEL, pp. 2-1 to 2-17, 2-64, 2-154, 47, 48, to 49, 62, 63.
MIPS32™ Architecture for Programmers vol. I: Introduction to the MIPS32™ Architecture, MIPS Technologies, Inc. (2002), 91 pages.
MIPS32™ Architecture for Programmers vol. II: The MIPS32™ Instruction Set, MIPS Technologies, Inc. (2002), 334 pages.
MIPS32™ Architecture for Programmers vol. III: The MIPS32™ Privileged Resource Architecture, MIPS Technologies, Inc. (2002), 137 pages.
MIPS64™ Architecture for Programmers vol. I: Introduction to the MIPS64™ Architecture, MIPS Technologies, Inc. (2002), 89 pages.
MIPS64™ Architecture for Programmers vol. II: The MIIPS64™ Instruction Set, MIPS Technologies, Inc. (2002), 344 pages.
MIPS64™ Architecture for Programmers vol. III: the MIPS64™ Privileged Resource Architecture, MIPS Technologies, Inc. (2002), 119 pages.
Chan Eddie P
MIPS Technologies Inc.
Petranek Jacob
Sterne Kessler Goldstein & Fox PLLC
LandOfFree
Instruction encoding for system register bit set and clear does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Instruction encoding for system register bit set and clear, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction encoding for system register bit set and clear will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4064305