Method for rate matching

Details Method for rate matching Method for rate matching

2003-02-14

2009-12-29

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S751000, C714S755000

Reexamination Certificate

active

07640486

ABSTRACT:
A method is provided for rate matching a number of input bits in a time interval to a fixed number of output bits in the time interval, whereby the input bits consist of a set of at least two different bit classes, each of the classes having a certain number of bits in the time interval, whereby the rate matching is performed in two rate matching stages, whereby the first rate matching stage operates only on a selection out of the set of different bit classes, thus establishing a proportion between the number of bits of the different classes, and the second rate matching stage operates on all bit classes such that the proportion is exactly or approximately maintained after the second rate matching stage and the fixed number of output bits consisting of bits of the different bit classes is achieved.

REFERENCES:
patent: 7000173 (2006-02-01), Buckley et al.
patent: 7372837 (2008-05-01), Kinjo et al.
patent: 2002/0006138 (2002-01-01), Odenwalder
patent: 1 176 725 (2002-01-01), None
patent: WO 99/52216 (1999-10-01), None
R1-02-0199, TR 25.858 “High Speed Downlink Packet access”, Espoo, Finland, Jan. 2002.
R1-02-0029, Siemens, “Physical Layer Hybrid ARQ Functionality for HSDPA” Espoo, Finland, Jan. 2002.
3GPP TS 25.212 V5.0.0 (Mar. 2003), “Multiplexing and channel coding (FDD) (Release 5)” 3GPP.

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