Flash memory device capable of reduced programming time

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185280

Reexamination Certificate

active

07492642

ABSTRACT:
A flash memory device and related method of operation are provided. The device generally comprises a word line voltage generator circuit configured to generate a word line voltage based on incremental step pulse programming; and a word line voltage controller circuit that controls the word line voltage generator circuit so that either the unit program time or the increment size of the word line voltage is varied according to the number of program data bits among the set of input data bits that the device will store in memory cells.

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Nobukata, H. et al., A 144-mb, eight-level NAND flash memory with optimized pulsewidth programming, IEEE Journal of Solid-State Circuits, May 2000, pp. 682-690, vol. 35, No. 5.
Kang-Deog Suh et al., TA7.5: A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme, Digest of Technical Papers, Feb. 16, 1995, pp. 128-130, IEEE ISSCC95.

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