Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-02-22
2009-06-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S002000
Reexamination Certificate
active
07552407
ABSTRACT:
A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers and the one or more inputs is computed. A second function of one or more of the one or more constraints over the one or more registers and the one or more inputs is computed. The inputs of the first function and the second function are existentially quantified. A bounded analysis is performed to determine if the one of the one or more targets may be hit while adhering to the constraints. A preimage of the inputs of the first function and a preimage of the inputs of the second function is existentially quantified to create a synthesizable preimage. The synthesizable preimage is simplified and synthesized to create an enlarged target. Verification of the enlarged target is performed.
REFERENCES:
patent: 6134516 (2000-10-01), Wang et al.
Bischoff et al., “Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking”, Second International Workshop on Bounded Model Checking (Jul. 2004).
Baumgartner Jason R.
Kanzelman Robert L.
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
International Business Machines - Corporation
Lin Aric
Siek Vuthe
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