Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-09-08
2009-08-18
Ghyka, Alexander G (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S424000, C438S427000, C438S640000, C438S947000, C257S906000, C257S907000, C257S908000, C257SE27087, C257SE27088, C257SE27131, C257SE27152, C257SE21656, C257SE21657, C257SE21658, C257SE21659
Reexamination Certificate
active
07575992
ABSTRACT:
A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface of a first oxide film pattern between a region in which a word line will be formed and a region in which a select source line will be formed is removed. Accordingly, the space can be increased and program disturbance in the region in which the word line will be formed can be prevented. Furthermore, a pattern having a line of 50 nm and a space of 100 nm or a pattern having a line of 100 nm and a space of 50 nm, which exceeds the limitation of the ArF exposure equipment, can be formed using a pattern, which has a line of 100 nm and a space of 200 nm and therefore has a good process margin and a good critical dimension regularity.
REFERENCES:
patent: 5328810 (1994-07-01), Lowrey et al.
patent: 5776816 (1998-07-01), Chen et al.
patent: 6861180 (2005-03-01), Chang
patent: 6955961 (2005-10-01), Chung
patent: 7202174 (2007-04-01), Jung et al.
patent: 2002/0168590 (2002-11-01), Hwang et al.
patent: 2005/0266652 (2005-12-01), Chudzik et al.
patent: 2006/0105273 (2006-05-01), Fukuda et al.
patent: 2006/0292497 (2006-12-01), Kim
patent: 2007/0158688 (2007-07-01), Caspary et al.
patent: 1158495 (1997-09-01), None
patent: 10-150027 (1998-06-01), None
patent: 1999-000089 (1999-01-01), None
patent: 2001-0003465 (2001-01-01), None
patent: 2001-0017089 (2001-03-01), None
patent: 1020010017086 (2001-03-01), None
patent: 2002-0024415 (2002-03-01), None
U.S. Appl. No. 11/475,319, filed Jun. 2006, Kim, Jong Hoon.
Sax et al., “Polysilicon Overfill Etch Back Using Wet Chemical Spin-Process Technology”, 1999, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 1999-2004.
Flounders, “Wet Etching of Silicon Nitride with Heated Phosphoric Acid”, Aug. 29, 2004, UCB Microlab, pp. 1-2.
Jung Woo Yung
Kim Jong Hoon
Chang Leonard
Ghyka Alexander G
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
LandOfFree
Method of forming micro patterns in semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming micro patterns in semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming micro patterns in semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4056747