Flash memory and method for determining logic states thereof

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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Details

C365S189090, C365S185190, C365S185200, C365S185210, C365S185220

Reexamination Certificate

active

07633797

ABSTRACT:
A method for determing the logic state of a memory cell of an array is provided. The array includes many word lines and bit lines. The method proceeds with the following steps. Firstly, a first voltage varing according to a sensing parasitic resistance of the memory cell is applied to the memory cell for a cell current. Next, a second voltage is applied to a reference cell corresponding to the memory cell for a reference current. Then, the cell current is compared with the reference current so as to determine the logic state of the memory cell.

REFERENCES:
patent: 6272043 (2001-08-01), Hollmer
patent: 2005/0024967 (2005-02-01), Matsuoka
patent: 2006/0023502 (2006-02-01), Cernea et al.
patent: 2007/0014144 (2007-01-01), Wicker
patent: 2007/0109889 (2007-05-01), Cernea et al.
patent: 2008/0043521 (2008-02-01), Liaw et al.
patent: 11-066876 (1999-03-01), None

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