Method for substantially uninterrupted cache readout

Details Method for substantially uninterrupted cache readout Method for substantially uninterrupted cache readout

2006-06-26

2009-06-09

Tran, Denise (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S168000, C365S189050

Reexamination Certificate

active

07546416

ABSTRACT:
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.

REFERENCES:
patent: 6243291 (2001-06-01), Cheah
patent: 7123521 (2006-10-01), Louie et al.
patent: 7369447 (2008-05-01), Louie et al.
patent: 7372744 (2008-05-01), Shiga et al.
patent: 2005/0232011 (2005-10-01), Lee et al.

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