Methods and systems for scheduling write destages based on a...

Details Methods and systems for scheduling write destages based on a... Methods and systems for scheduling write destages based on a...

2006-12-15

2009-08-18

Peugh, Brian R (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

07577787

ABSTRACT:
Methods and systems are disclosed that relate to scheduling the processing of I/O requests in a cache for a plurality of logical devices associated with the cache. An exemplary method includes identifying a minimum target number of write destages to be performed with respect to a logical device per unit time. In identifying the minimum target number, factors such as a write pending count and an average queue length of writes pending may be considered. The method further includes enforcing the target minimum number of write destages. A disclosed method of enforcing the target includes tracking the number of write destages performed on the logical device and increasing a priority for a write request to the logical device when the minimum target number of write destages is not met.

REFERENCES:
patent: 6141731 (2000-10-01), Beardsley et al.
patent: 6189080 (2001-02-01), Ofer
patent: 6904470 (2005-06-01), Ofer et al.
patent: 2007/0220201 (2007-09-01), Gill et al.
U.S. Appl. No. 11/154,234, entitled “Physical Based Scheduler,” filed Jun. 16, 2005.

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