Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-31
2008-12-30
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S014000, C702S069000, C702S106000, C702S191000
Reexamination Certificate
active
07472362
ABSTRACT:
A method of minimizing phase noise is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Further, the first phase noise is compared with the second phase noise. If the phase noises are about the same, it is determined that the noise source is from an algorithm of a random number generator, the second circuit is modified to optimize the performances of the integrated circuit, and the modified second circuit is copied to the first circuit. If the phase noises are different, it is determined that a source of the phase noise is at least one of a power supply coupling and a substrate coupling in the integrated circuit.
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International Business Machines - Corporation
Kik Phallaka
Zilka-Kotab, PC
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