Method for calibration of memory devices, and apparatus thereof

Details Method for calibration of memory devices, and apparatus thereof Method for calibration of memory devices, and apparatus thereof

2006-03-30

2008-12-16

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S154000

Reexamination Certificate

active

07467255

ABSTRACT:
A memory controller for a memory device. The memory controller includes a first sensor, a second sensor, and a command generator. The first sensor detects an operating environment of the memory controller. The second sensor detects an operating status of the memory controller. The command generator is coupled to the first sensor, the second sensor, and the memory device, and facilitates the sending of commands to the memory device to calibrate the memory device when the operating environment detected by the first sensor meets a first prerequisite, and the operating status detected by the second sensor meets a second prerequisite.

REFERENCES:
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patent: 6885959 (2005-04-01), Salmon et al.
patent: 2005/0226080 (2005-10-01), Lee
patent: 2006/0044047 (2006-03-01), Porter
patent: 2006/0214739 (2006-09-01), Kang
“DDR2 SDRAM Specification.”, Jedec Standard, Jan. 2005, pp. I-IV, I-104, JESD79-2B, JEDEC Solid State Technology Association, Arlington, VA, USA.

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