Active biasing in metal oxide semiconductor (MOS)...

Details Active biasing in metal oxide semiconductor (MOS)... Active biasing in metal oxide semiconductor (MOS)...

2005-05-12

2008-12-30

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S087000

Reexamination Certificate

active

07471107

ABSTRACT:
Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.

REFERENCES:
patent: 5510729 (1996-04-01), Reymond
patent: 5959492 (1999-09-01), Khoury et al.
patent: 6114898 (2000-09-01), Okayasu
patent: 6288604 (2001-09-01), Shih et al.
patent: 6507218 (2003-01-01), To et al.
patent: 6577154 (2003-06-01), Fifield et al.

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