Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-03-27
2008-11-11
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07451413
ABSTRACT:
Methods, systems and computer program products for automatically minimizing leakage current in a circuit design can include post layout delay information of a circuit that meets timing limits is analyzed. The circuit can include a first type of cells, and the first type of cells each can include a first threshold voltage and a first leakage current. After post layout delay information are analyzed, a non-speed-critical path in the circuit is selected. A dopant implant level of at least one transistor in at least one cell along the selected non-speed-critical path is modified to change the first threshold voltage of the transistor to a second threshold voltage and the first leakage current of the transistor to a second leakage current. In some implementations, the magnitude of the first threshold voltage is less than a magnitude of the second leakage current and the total leakage current of the circuit is reduced.
REFERENCES:
patent: 4816893 (1989-03-01), Mayer et al.
patent: 4845047 (1989-07-01), Holloway et al.
patent: 5774367 (1998-06-01), Reyes et al.
patent: 6075932 (2000-06-01), Khouja et al.
patent: 6111427 (2000-08-01), Fujii et al.
patent: 6209122 (2001-03-01), Jyu et al.
patent: 6462978 (2002-10-01), Shibata et al.
patent: 6687888 (2004-02-01), Chen
patent: 6693331 (2004-02-01), Mistry et al.
patent: 2002/0141234 (2002-10-01), Kaviani
patent: 2002/0144223 (2002-10-01), Usami et al.
patent: 2003/0163792 (2003-08-01), Xie et al.
patent: WO 02/080368 (2002-10-01), None
Smith, M.J.S., ed. “Introduction to ASICS,” Chapter 1In, Application-Specific Integrated Circuits. Addison-Wesley; Boston, MA, 1997, pp. 16-17.
Smith, M.J.S., ed. “Low-Level Design Entry,” Chapter 9In, Application-Specific Integrated Circuits. Addison-Wesley; Boston, MA, 1997, pp. 334-337.
Lin Sun J
Marvell International Ltd.
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