Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-24
2008-12-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07472368
ABSTRACT:
A method is provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.
REFERENCES:
patent: 2002/0073384 (2002-06-01), Buffet et al.
patent: 2003/0212980 (2003-11-01), Frank et al.
patent: 2004/0015806 (2004-01-01), Frank et al.
patent: 2004/0145033 (2004-07-01), McElvain
patent: 2004/0219688 (2004-11-01), Churchill et al.
patent: 2004/0222514 (2004-11-01), Crane et al.
patent: 2006/0236276 (2006-10-01), Frank et al.
Bartley Gerald Keith
Becker Darryl John
Dahlen Paul Eric
Germann Philip Raymond
Maki Andrew Benson
Chiang Jack
International Business Machines - Corporation
Memula Suresh
Pennington Joan
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