Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-10-25
2008-11-18
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100
Reexamination Certificate
active
07453753
ABSTRACT:
A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.
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Hynix / Semiconductor Inc.
Kaminski Jeffri A.
Phung Anh
Venable LLP
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