Programming method for flash memory capable of compensating...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185280, C365S185240

Reexamination Certificate

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07463526

ABSTRACT:
A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined region of threshold voltage distribution each corresponding to at least two of the states, wherein predetermined regions of the respective at least two states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and simultaneously programming detected memory cells of the at least two states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

REFERENCES:
patent: 2005/0105337 (2005-05-01), Cohen et al.
patent: 10214492 (1998-08-01), None
patent: 2000222893 (2000-08-01), None
patent: 1020050018943 (2005-02-01), None
patent: 1020060107689 (2006-10-01), None
patent: 2004006266 (2004-01-01), None

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