Reconstruction of signal timing in integrated circuits

Details Reconstruction of signal timing in integrated circuits Reconstruction of signal timing in integrated circuits

2007-02-21

2008-11-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189080, C365S233100

Reexamination Certificate

active

07453746

ABSTRACT:
Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

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