Method for fabricating wafer level semiconductor package...

Details Method for fabricating wafer level semiconductor package... Method for fabricating wafer level semiconductor package...

2006-10-12

2008-11-04

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S122000, C257SE21494, C257SE21499, C257SE21503, C257SE21508, C257SE23101

Reexamination Certificate

active

07445957

ABSTRACT:
A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

REFERENCES:
patent: 5868887 (1999-02-01), Sylvester et al.
patent: 6020637 (2000-02-01), Karnezos
patent: 6154366 (2000-11-01), Ma et al.
patent: 6271469 (2001-08-01), Ma et al.
patent: 6498387 (2002-12-01), Yang
patent: 7170152 (2007-01-01), Huang et al.

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