Semiconductor memory device having delay circuit

Details Semiconductor memory device having delay circuit Semiconductor memory device having delay circuit

2006-11-14

2008-11-11

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189070, C365S189090

Reexamination Certificate

active

07450446

ABSTRACT:
Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.

REFERENCES:
patent: 6181637 (2001-01-01), Nishimura et al.
patent: 6469557 (2002-10-01), Hirabayashi
patent: 6629251 (2003-09-01), Anderson et al.
patent: 6738296 (2004-05-01), Sung et al.
patent: 7012847 (2006-03-01), Song
patent: 2000-285672 (2000-10-01), None

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