Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-06
2008-12-09
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C257S751000, C257S758000, C257S774000, C438S622000, C438S637000
Reexamination Certificate
active
07464352
ABSTRACT:
A semiconductor device100has a configuration having a via124formed on a first interconnect112. A method for designing the semiconductor device100includes: calculating an anticipated value xopenof a dimension of a growing region of a void150expanding in a stress induced voiding (SIV)-ensured time topenat a predetermined temperature, assuming that the void150grows from an origin in a copper interconnect (interconnect metallic film110); and determining a geometric factor of the via124by comparing a dimension of a contacting region between a first interconnect112and the via124with the anticipated value xopen. The dimension of the contacting region may be presented as d+h (where d represents a diameter of a via124, and h represents a buried depth that the via124is buried within the first interconnect112).
REFERENCES:
patent: 6513389 (2003-02-01), Suresh et al.
patent: 6816995 (2004-11-01), Yokogawa
patent: 6823500 (2004-11-01), Ganesh et al.
patent: 7033924 (2006-04-01), Ogawa et al.
patent: 7247946 (2007-07-01), Bruley et al.
patent: 7315998 (2008-01-01), Fischer et al.
patent: 2004/0268275 (2004-12-01), Cappelletti et al.
patent: 2005/0006770 (2005-01-01), Sukharev et al.
patent: 2006/0190846 (2006-08-01), Hichri et al.
patent: 7-235596 (1995-09-01), None
Ogawa et al.; “Stress-induced voiding under vias connected to wide Cu metal leads”; Apr. 7-11, 2002; Reliability Physics Symposium Proceedings, 2002. 40th Annual; pp. 312-321.
Oshima et al.; “Improvement of thermal stability of via resistance in dual damascence copper interconnection” Dec. 10-13, 2000; Electron Devices Meeting, 2000. IEDM Technical Digest. International; pp. 123-126.
Park et al.: “Mechanisms of stress-induced voids in multi-level Cu interconnects”; Jun. 3-5, 2002; Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International; pp. 130-132.
Choy et al.; “Effects of capillary forces on the global thinning of copper metallization under electromigration stress”; Oct. 18-21, 2004; Integrated Reliability Workshop Final Report, 2004 IEEE International; pp. 75-78.
Ueki et al.; “Effects of Ti addition on via reliability in Cu dual damascene interconnects”; Nov. 2004; Electron Devices, IEEE Transactions on; vol. 51, Issue 11, pp. 1883-1891.
Takashi Suzuki, “Evaluations on Positron Annihilation for Defects in the Plated Cu,” Proceedings of the 10thMeeting, The Japan Society of Applied Physics, Thin Film Surface Physics Division, Jul. 15-16, 2004, pp. 22-23.
Mads R. Sørensen, et al. “Diffusion Mechanisms in Cu Grain Boundaries,” The American Physical Society, Physical Review B, vol. 62, No. 6, Aug. 1, 2000, pp. 3658-3673.
Chang-Hee Lee, et al. “Residual Stress Effect on Self-Annealing of Electroplated Copper,” Jpn. J. Appl. Phys., vol. 42, 2003, pp. 4484-4488.
NEC Electronics Corporation
Rossoshek Helen
Sughrue & Mion, PLLC
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