Debugging mechanism and debugging register

Details Debugging mechanism and debugging register Debugging mechanism and debugging register

2006-04-25

2008-12-30

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S047300

Reexamination Certificate

active

07472310

ABSTRACT:
The present invention aims at providing a debugging mechanism capable of detecting erroneous read access to a bus slave caused by a synchronization control infringement between bus masters due to a failure of software. Each of a dirty detector and a coherency error detector is used as a detector for monitoring a bus control unit and, during a period that write access corresponding to optionally designated conditions is present on a write buffer, detecting read access corresponding to conditions equal to the aforementioned conditions. A bus master includes a debugging unit. The debugging unit receives a coherency error notification from the coherency error detector to generate a debugging event, breaks an operation of the bus master, and performs various debugging operations while using the debugging event as a trigger.

REFERENCES:
patent: 5481670 (1996-01-01), Hatashita et al.
patent: 6061600 (2000-05-01), Ying
patent: 6070205 (2000-05-01), Kato et al.
patent: 6147967 (2000-11-01), Ying et al.
patent: 2004/0107265 (2004-06-01), Yasunaga
patent: 05-136787 (1993-06-01), None

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