Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2006-12-21
2008-11-11
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000
Reexamination Certificate
active
07449918
ABSTRACT:
To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters300and200of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter300is used as a level converting unit. A voltage level of a first control signal CS1output from an output node no1of the first inverter300is forcibly dropped down by a voltage dropping circuit CONT1so as to accelerate the operation of the second inverter200. As a result, the inversion of the level of an output signal of the first inverter300is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter200are reduced so as to suppress an increase in a circuit area.
REFERENCES:
patent: 6700429 (2004-03-01), Kanno et al.
patent: 6940332 (2005-09-01), Yamahira et al.
patent: 7085177 (2006-08-01), Savage
patent: 2004-153524 (2004-05-01), None
Mori Toshiki
Yamahira Seiji
Cho James H
McDermott Will & Emery LLP
Panasonic Corporation
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