Semiconductor memory device having layout area reduced

Details Semiconductor memory device having layout area reduced Semiconductor memory device having layout area reduced

2007-05-08

2008-11-18

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000

Reexamination Certificate

active

07453126

ABSTRACT:
A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.

REFERENCES:
patent: 5352916 (1994-10-01), Kiyono et al.
patent: 6333877 (2001-12-01), Nagaoka et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device having layout area reduced does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having layout area reduced, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having layout area reduced will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4040152