Method for SRAM bitmap verification

Details Method for SRAM bitmap verification Method for SRAM bitmap verification

2005-10-07

2008-12-16

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07467363

ABSTRACT:
A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit “defect” is intentionally created in the physical layout. Then, the new electrical schematic is extracted from the modified physical layout. Subsequently, if the design “defect” which was created is temporary, the new electrical schematic is simulated, the logical address of the “defect” is determined, and the extracted logical address is compared to the expected address to verify the logical to physical correlation. Alternatively, if the design “defect” which was created is permanent, after the new electrical schematic is extracted from the modified physical layout, the product is fabricated and the known design “defect” location is used to correlate to the electrically-tested defect logical location.

REFERENCES:
patent: 5884065 (1999-03-01), Takasaki
patent: 6510533 (2003-01-01), Siek et al.
patent: 2004/0205681 (2004-10-01), Nozuyama
patent: 2006/0005094 (2006-01-01), Nozuyama

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