Supporting cyclic redundancy checking for PCI-X

Details Supporting cyclic redundancy checking for PCI-X Supporting cyclic redundancy checking for PCI-X

2002-09-12

2008-11-04

Chaudry, Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C710S063000

Reexamination Certificate

active

07447975

ABSTRACT:
A cyclic redundancy check (CRC) mechanism for the extensions (PCI-X) to the Peripheral Component Interconnect (PCI) bus system used in computer systems is fully backward compatible with the full PCI-X protocol. CRC check-bits are inserted to provide error detection capability for the header address and attribute phases, and for burst and DWORD transaction data phases. The CRC check-bits are inserted into unused attribute or clock (or target response) phases, or into reserved or reserved drive high portions (bits) of the address/data (AD), command/byte enable (C/BE#), or into the parity lanes of the PCI-X phases.

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