Patterned structures fabricated by printing mask over...

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S149000

Reexamination Certificate

active

07459400

ABSTRACT:
A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.

REFERENCES:
patent: 5521032 (1996-05-01), Imai et al.
patent: 6127725 (2000-10-01), Harris
patent: 6348295 (2002-02-01), Griffith et al.
patent: 6742884 (2004-06-01), Wong et al.
patent: 6818959 (2004-11-01), Montelius et al.
patent: 6872320 (2005-03-01), Wong et al.
patent: 6890050 (2005-05-01), Ready et al.
patent: 6913944 (2005-07-01), Hirai
patent: 6972261 (2005-12-01), Wong et al.
patent: 7109118 (2006-09-01), Cohen et al.
patent: 2003/0134516 (2003-07-01), Wong et al.
patent: 2005/0032362 (2005-02-01), Cohen et al.
patent: 2005/0136358 (2005-06-01), Paul et al.
patent: 2005/0142293 (2005-06-01), Ready et al.
patent: 2005/0158880 (2005-07-01), Ostuni et al.
patent: 2006/0003475 (2006-01-01), Adewole et al.
patent: 2006/0057851 (2006-03-01), Wong et al.
patent: 2006/0105492 (2006-05-01), Veres et al.
patent: 2006/0131266 (2006-06-01), Street et al.
patent: 2006/0131563 (2006-06-01), Salleo et al.
patent: 2007/0026585 (2007-02-01), Wong et al.
patent: 2007/0082438 (2007-04-01), Li et al.
patent: 2007/0145362 (2007-06-01), Wolkin et al.
patent: 2007/0161163 (2007-07-01), Hirai
patent: 2007/0166874 (2007-07-01), Lin et al.
Thomasson D.B., “Fully Self-Aligned Tri-layer a-Si:H Thin-Film Transistors with Deposited Doped Contact Layer” IEEE Electron Device Letters, vol. 19, No. 4 1998 p. 124-126.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Patterned structures fabricated by printing mask over... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Patterned structures fabricated by printing mask over..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Patterned structures fabricated by printing mask over... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4034528

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.