Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-02
2008-11-25
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07458047
ABSTRACT:
A method of designing a layout of a functional block and an on-chip capacitor in a semiconductor integrated circuit, includes the steps of (a) designing a layout of a capacitor/block including a functional block, and an on-chip capacitor having a predetermined capacity and disposed adjacent to the functional block, (b) judging whether the layout resulted from the step (a) satisfies predetermined requirements, (c) designing again a layout of a capacitor/block including an on-chip capacitor having a capacity smaller than a capacity of an on-chip capacitor of the previously designed capacitor/block, only when the layout resulted from the step (a) is judged not to satisfy the predetermined requirements, and (d) judging whether the layout resulted from the step (c) satisfies the predetermined requirements. The steps (c) and (d) are repeatedly carried out until the layout satisfies the predetermined requirements.
REFERENCES:
patent: 5631492 (1997-05-01), Ramus et al.
patent: 5883814 (1999-03-01), Luk et al.
patent: 6037621 (2000-03-01), Wilson
patent: 6320237 (2001-11-01), Assaderaghi et al.
patent: 6370678 (2002-04-01), Culler
patent: 6424058 (2002-07-01), Frech et al.
patent: 6480992 (2002-11-01), Runyon
patent: 6608365 (2003-08-01), Li et al.
patent: 6635916 (2003-10-01), Aton
patent: 6777304 (2004-08-01), Assaderaghi et al.
patent: 6897505 (2005-05-01), Aton
patent: 6980414 (2005-12-01), Sutardja
patent: 7086026 (2006-08-01), Berry et al.
patent: 7116544 (2006-10-01), Sutardja
patent: 7346877 (2008-03-01), Berry et al.
patent: 2001/0046125 (2001-11-01), Rehm et al.
patent: 2002/0008290 (2002-01-01), Assaderaghi et al.
patent: 2002/0024087 (2002-02-01), Aton
patent: 2004/0004241 (2004-01-01), Aton
patent: 2004/0075152 (2004-04-01), Barna et al.
patent: 2004/0199882 (2004-10-01), Cao et al.
patent: 2006/0200783 (2006-09-01), Berry et al.
patent: 11-168177 (1999-06-01), None
patent: 2001-351985 (2001-12-01), None
patent: 2004-86881 (2004-03-01), None
Hiroshi et al., Japanese Patent No. JP 2001-351985, published on Dec. 21, 2001, translated in English using Automated English translation provided by the Japanese Patent Office, translated on Jan. 5, 2008, pp. 1-25.
Heydari et al., “Ground Bounce in Digital VLSI Circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 2, Apr. 2003, pp. 180-193.
Fu et al., “Decoupling Capacitor Allocation for Power Delivery Network Noise Reduction Based on Standard Cell Layouts”, Proceedings of 5th International Conference on ASIC, vol. 1, Oct. 21-24, 2003, pp. 101-104.
Ghonemia et al., “Formal Derivation of Optimal Active Shiedling for Low-Power On-Chip Buses”, IEEE/ACM International Conference on Computer Aided Design,Nov. 7-11, 2004, pp. 800-807.
Wang et al., “On-Chip Decoupling Capacitor Design to Reduce Switching Noise-Induced Instability in CMOS/SOI VLSI”, Proceedings of 1995 IEEE International SOI Conference, Oct. 3-5, 1995, pp. 100-101.
Pandini et al., “Design Methodologies and Architecture Solutions for High-Performance Interconnects”, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 11-13, 2004, pp. 152-159.
Kik Phallaka
NEC Corporation
Young & Thompson
LandOfFree
Method of designing layout of semiconductor integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of designing layout of semiconductor integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing layout of semiconductor integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4030687