Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-02-02
2008-11-18
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S103000, C326S037000, C326S038000
Reexamination Certificate
active
07454556
ABSTRACT:
A method is provided to program a memory device through a JTAG interface of an attached component with programmable logic, wherein the memory device does not have a JTAG interface. Initially, programming hardware to provide for programming of the attached memory is downloaded into the component via the component's JTAG interface. The programmed component then becomes a serial data link between the JTAG port attached to a host programmer and a non-JTAG port attached to the memory device. The circuitry downloaded or programmed into the component controls the timing and the protocol to program the external memory.
REFERENCES:
patent: 5635855 (1997-06-01), Tang
patent: 5999014 (1999-12-01), Jacobson et al.
patent: 6044025 (2000-03-01), Lawman
patent: 6097211 (2000-08-01), Couts-Martin et al.
patent: 6102963 (2000-08-01), Agrawal
patent: 6259271 (2001-07-01), Couts-Martin et al.
patent: 6336209 (2002-01-01), Nishihara et al.
patent: 6714040 (2004-03-01), Jacobson et al.
patent: 6898776 (2005-05-01), Jacobson et al.
patent: 7023239 (2006-04-01), Jacobson et al.
patent: 7047467 (2006-05-01), Khu et al.
patent: 2006/0038586 (2006-02-01), Xia et al.
U.S. Appl. No. 10/810,032, filed Mar. 26, 2004, Knapp.
U.S. Appl. No. 10/043,637, filed Jan. 9, 2002, Khu et al.
The Institute of Electrical and Electronics Engineers, Inc.; “IEEE Standard for In-System Configuration of Programmable Devices”, IEEE Std. 1532-2002, Jan. 10, 2003, pp. 1-141, available from IEEE, 3 Park Avenue, New York, NY 10016-5997.
The Institute of Electrical and Electronics Engineers, Inc.; “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std 1149.1-1990, Feb. 17, 1993, pp. 1-127, available from IEEE, 3 Park Avenue, New York, NY 10016-5997.
Xilinx, Inc.; U.S. Appl. No. 10/606,728 by Bridgford on Jun. 26, 2003.
Xilinx, Inc.; U.S. Appl. No. 10/955,807 by Jacobson on Sep. 29, 2004.
Rick Folea; “Programming Flash Memory from FPGAs and CPLDs Using the JTAG Port”; Xilinx Xcell Journal; Summer 2004; pp. 1-3.
Kris Chaplin; “Reconfiguring Block RAMs—Part 1 and Part 2”; Jul. 17, 2003; downloaded from http://www.xilinx.com/xInx/xweb/xil—tx—display.jsp?sTechX—ID=rs—blockRAM; pp. 1-9.
Lo Kenneth M
Maunu LeRoy D.
Sough Hyung
Ward Thomas A.
Xilinx , Inc.
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