Split-gate flash memory cell structure

Details Split-gate flash memory cell structure Split-gate flash memory cell structure

1997-12-24

1999-05-25

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257325, H01L 29788

Patent

active

059071729

ABSTRACT:
A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating dielectric layer is then formed over the first gate. The insulating dielectric has a lens-shaped cross-section located above the sharp corner. Next, a second gate is formed over the insulating dielectric layer, and surrounded the first gate. A first doped region is formed in the substrate below the sharp corner. Then, a second doped region is formed in the substrate located on the other side of the first gate just opposite the first doped region, furthermore, the second doped region is separated from the first gate by a distance. There is a channel region between the first doped region and the second doped region, and the sharp corner of this invention is located above the semiconductor substrate outside the channel region.

REFERENCES:
patent: 5045488 (1991-09-01), Yeh
patent: 5289026 (1994-02-01), Ong

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