Secure execution mode exceptions

Electrical computers and digital processing systems: support – Computer program modification detection by cryptography

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C713S189000

Reexamination Certificate

active

07451324

ABSTRACT:
A method and system for handling a security exception. The method includes creating a security exception stack frame in secure memory at a base address. The method also includes writing a faulting code sequence address and one or more register values into the security exception stack frame, and executing a plurality of security exception instructions.

REFERENCES:
patent: 5369770 (1994-11-01), Thomason et al.
patent: 5535397 (1996-07-01), Durante et al.
patent: 5684948 (1997-11-01), Johnson et al.
patent: 5937186 (1999-08-01), Horiguchi et al.
patent: 6330666 (2001-12-01), Wise et al.
patent: 6697959 (2004-02-01), Andress et al.
patent: 6725362 (2004-04-01), Kahn et al.
patent: 6792499 (2004-09-01), Eldredge
patent: 6957332 (2005-10-01), Ellison et al.
International PCT Search Report PCT/US 02/40219 dated Mar. 27, 2003.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Secure execution mode exceptions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Secure execution mode exceptions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Secure execution mode exceptions will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4021958

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.