Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-08-17
2008-08-05
Elmore, Stephen C (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S122000, C711S203000, C711S207000
Reexamination Certificate
active
07409524
ABSTRACT:
The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
REFERENCES:
patent: 5008813 (1991-04-01), Crane et al.
patent: 5809563 (1998-09-01), Yamada et al.
patent: 5860146 (1999-01-01), Vishin et al.
patent: 5870599 (1999-02-01), Hinton et al.
patent: 6427188 (2002-07-01), Lyon et al.
patent: 7111145 (2006-09-01), Chen et al.
patent: 2004/0015752 (2004-01-01), Patella et al.
Jacob, Bruce, Virtual Memory Systems and TLB Structures, pp. 1-17, 2001 CRC Press.
Intel Itanium Architecture Software Developer's Manual, vol. 2: System Architecture, Revision 2.1, Oct. 2002.
Next Generation Itanium Processor Overview, Intel Developer Forum, Fall 2001.
Computer Organization and Design The Hardware/Software Interface, Second Edition, Chapter 7, pp. 540-635, 1998.
Bhatia Rohit
Brummel Karl
Safford Kevin
Elmore Stephen C
Hewlett--Packard Development Company, L.P.
LandOfFree
System and method for responding to TLB misses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for responding to TLB misses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for responding to TLB misses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4018593