Strained MOSFETs on separated silicon layers

Details Strained MOSFETs on separated silicon layers Strained MOSFETs on separated silicon layers

2006-08-10

2008-10-14

Tran, Long K (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S244000, C257S466000, C257SE29020, C257SE21550, C257SE21551, C257SE21553, C257SE21554, C438S294000, C438S297000, C438S682000

Reexamination Certificate

active

07436030

ABSTRACT:
A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

REFERENCES:
patent: 7214963 (2007-05-01), Choi et al.
patent: 2003/0127697 (2003-07-01), Ohta et al.
Singer, “Dual Liner Stresses NMOS and PMOS,” Reed Business Information, 2006, pp. 1-2.
Tilke et al., “Using an STI gap-fill technology with a high-aspect-ratio process for 45-nm CMOS and beyond,” Micro Magazine, May 2006, pp. 1-12.

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