Method and apparatus for performing synthesis to improve...

Details Method and apparatus for performing synthesis to improve... Method and apparatus for performing synthesis to improve...

2005-01-07

2008-10-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07441223

ABSTRACT:
A method for designing a system on a programmable logic device (PLD) includes implementing a first network of logic elements (LEs) and a second network of LEs with a combined network of LEs that performs a same functionality but utilizes a fewer number of LEs.

REFERENCES:
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6408422 (2002-06-01), Hwang et al.
patent: 7111273 (2006-09-01), Ganesan et al.
patent: 7124392 (2006-10-01), Sharma
patent: 7194723 (2007-03-01), Hwang et al.
patent: 7243329 (2007-07-01), Chua et al.
patent: 7249329 (2007-07-01), Baeckler et al.
patent: 2004/0133869 (2004-07-01), Sharma
patent: 2005/0177808 (2005-08-01), Dewan

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