Limited switch dynamic logic cell based register

Details Limited switch dynamic logic cell based register Limited switch dynamic logic cell based register

2007-10-24

2008-08-19

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S121000

Reexamination Certificate

active

07414436

ABSTRACT:
A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

REFERENCES:
patent: 6023179 (2000-02-01), Klass
patent: 6310499 (2001-10-01), Radjassamy
patent: 6693459 (2004-02-01), Nedovic et al.
patent: 6809570 (2004-10-01), Francom
patent: 7161390 (2007-01-01), Aipperspach et al.

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