Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2006-02-24
2008-08-05
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S014000, C710S022000, C710S040000, C710S310000
Reexamination Certificate
active
07409476
ABSTRACT:
A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. Also provided is a data packet format for transferring data, which comprises of an Endpoint Transfer Descriptor (“ETD”) that includes an EndPoint Descriptor and a Transfer Descriptor, wherein the host system programs the parameters of a communication channel for a particular Endpoint. Also included is a technique for partitioning a memory storage device into a first memory buffer and a second memory buffer; wherein the size of the first and second memory buffer may be programmed by the host system and the first and/or second memory buffer may contain more than one USB packet.
REFERENCES:
patent: 4268908 (1981-05-01), Logue et al.
patent: 5933611 (1999-08-01), Shakkarwar
patent: 6349354 (2002-02-01), Garney
patent: 6842797 (2005-01-01), Lawande
patent: 2002/0116565 (2002-08-01), Wang et al.
patent: WO 2004/102406 (2004-11-01), None
Liang Ping
Wang Jing
Wu Zong Liang
Auve Glenn A.
Klein O'Neill & Singh, LLP
Oxford Semiconductor, Inc.
Patel Nimesh G
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