Method for error reduction in lithography

Details Method for error reduction in lithography Method for error reduction in lithography

2004-04-20

2008-10-28

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C700S121000, C382S144000

Reexamination Certificate

active

07444616

ABSTRACT:
The present invention relates to a method and a system for predicting and/or measuring and correcting geometrical errors in lithography using masks, such as large-area photomasks or reticles, and exposure stations, such as wafer steppers or projection aligners, printing the pattern of said masks on a workpiece, such as a display panel or a semiconductor wafer. A method to compensate for process variations when printing a pattern on a workpiece, including determining a two-dimensional CD profile in said pattern printed on said workpiece, generating a two-dimensional compensation file to equalize fluctuations in said two-dimensional CD-profile, and patterning a workpiece with said two-dimensional compensation file.

REFERENCES:
patent: 5655110 (1997-08-01), Krivokapic et al.
patent: 5657235 (1997-08-01), Liebmann et al.
patent: 6021009 (2000-02-01), Borodovsky et al.
patent: 6424879 (2002-07-01), Chilese et al.

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