Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-03-15
2008-10-14
Puente, Emerson C (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S004110, C714S005110
Reexamination Certificate
active
07437602
ABSTRACT:
The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.
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patent: 6735121 (2004-05-01), Yoshida
patent: 6922802 (2005-07-01), Kim et al.
patent: 7050252 (2006-05-01), Vallis
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patent: 2004/0125716 (2004-07-01), Ko et al.
patent: 2002-182989 (2002-06-01), None
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Asari Shinsuke
Kanamori Motoki
Nakamura Yasuhiro
Shinagawa Chiaki
Shiraishi Atsushi
Miles & Stockbridge P.C.
Puente Emerson C
Renesas Technology Corp.
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