Memory timing model with back-annotating

Details Memory timing model with back-annotating Memory timing model with back-annotating

2005-12-19

2008-08-19

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C714S718000

Reexamination Certificate

active

07415686

ABSTRACT:
A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.

REFERENCES:
patent: 6249901 (2001-06-01), Yuan et al.
patent: 6553552 (2003-04-01), Khan et al.
patent: 6813201 (2004-11-01), Zarrineh et al.
patent: 7031898 (2006-04-01), Jain et al.

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