Bus system for shadowing registers

Details Bus system for shadowing registers Bus system for shadowing registers

1996-07-19

1998-08-11

Sheikh, Ayaz R.

395495, 395293, G06F 1300

Patent

active

057939950

ABSTRACT:
The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

REFERENCES:
patent: 5640570 (1997-06-01), St. Clair et al.
patent: 5642489 (1997-06-01), Bland et al.
DMA Support on the "PCIway", Aug. 2, 1995, Version 5.4, Preliminary, pp. 2-16.
PCI Specification, Rev. 2.1, A100910-940, pp. 37-72, Aug. 3, 1995.

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